1. Field of the Invention
The present invention relates to a semiconductor apparatus having a multi-layer wiring structure and a method of fabricating the same. In particular, this invention relates to a semiconductor apparatus having fine wiring and a contact plug between wiring layers formed by means of lithographical techniques and to a method of fabricating the semiconductor apparatus.
2. Description of the Related Art
In a currently prevailing method of forming wiring, a conductor film deposited uniformly on an insulating film is processed by means of lithography and etching and then insulating films are formed between and over wiring elements by means of CVD. In this method, however, it becomes difficult to achieve an exact wiring process or fill insulating films among wiring elements as the width of each wiring element and the pitch of wiring elements decrease due to higher integration density of semiconductor integrated circuits. To solve this problem, attention has been paid to a so-called Damascene method in which wiring is formed by burying conductor elements in grooves formed in insulating films.
FIGS. 1 to 3 illustrate the steps of a wiring forming process to which the Damascene method is applied.
As is shown in FIG. 1, a field oxide film 12 is formed on a silicon substrate 11. For example, a MOS transistor is formed in a device region surrounded by the field oxide film. Silicon oxide films 13 and 14 are formed over the entire surface of the silicon substrate 11. The silicon oxide film 14 is processed by a photolithographical step and an etching step to form grooves 31 in which wiring is formed (hereinafter referred to as "wiring grooves 31"). Subsequently, the silicon oxide film 13 is processed by a photolithographical step and an etching step to form contact holes 32 extending downward from the bottoms of the wiring grooves 31 to a gate electrode 21 and source/drain regions 22a and 22b of the MOS transistor.
As is shown in FIG. 2, a conductor film 16 is formed over the entire surface of the resultant structure. The conductor film 16 is polished by means of CMP (chemical mechanical polishing) until the conductor film 16 is left only within the wiring grooves 31 and contact holes 32.
Then, as shown in FIG. 3, silicon oxide films 17 and 18 are formed on the silicon oxide film 14 and conductor film 16. The silicon oxide film 18 is processed by a photolithographical step and an etching step to form grooves 33 in which wiring is formed (hereinafter referred to as "wiring grooves 33"). Subsequently, the silicon oxide film 17 is processed by a photolithographical step and an etching step to form contact holes 34 extending downward from the bottoms of the wiring grooves 33 to the conductor film 16. Then, a conductor film 20 is formed over the entire surface of the resultant structure. The conductor film 20 is polished by means of CMP (chemical mechanical polishing) until the conductor film 20 is left only within the wiring grooves 33 and contact holes 34. A wiring protection film 19 is formed on the silicon oxide film 18 and conductor film 20.
In the above wiring forming process, the photolithographical and etching steps are carried out to form the wiring grooves 31 and 33 for the formation of wiring and the contact holes 32 and 34 formed in the bottoms of wiring grooves 31 and 33 for contact between the lower wiring layer and the upper wiring layer.
In the photolithographical steps of forming the contact holes 32 and 34, as shown in FIG. 4, formation of a resist film 35 with high resolution is difficult due to the presence of stepped portions of the wiring grooves 31 and 33.
In addition, the bottom face of side face of each groove 31, 33 formed in the silicon oxide film 14, 18 are perpendicular to each other, and also the bottom face and side face of each contact hole 32, 34 formed in the silicon oxide film 13, 17 are perpendicular to each other. As a result, coverage of the conductor film 16 and 20 is degraded.
The problem illustrated in FIG. 4, i.e. the difficulty in obtaining resist film 35 with high resolution, will now be described in greater detail with reference to other FIGURES.
FIGS. 5 to 7 are cross-sectional perspective views illustrating in succession the steps of a conventional process for forming a contact hole.
As is shown in FIG. 5, a lower wiring element 42 is formed in an insulating film 41 provided on a semiconductor substrate. An insulating film 43, an etching stopper film 45 and an insulating film 44 are laminated in succession on the insulating film 41 including the lower wiring element 42. A groove 46 for formation of an upper wiring element is formed in a predetermined region of the insulating film 45. The wiring groove 46 is located above the lower wiring element 42. Anisotropical etching for forming the groove 46 is stopped by the etching stopper film 44. The exposed etching stopper film 44 is removed.
Then, a photolithographical step is initiated, as shown in FIG. 6. A resist film 47 is applied to the insulating film 45 with the groove 46. That portion of the resist film 47, which is located in a predetermined region of the groove 46, needs to be removed by exposing and developing the resist film 47 with use of a patterning mask (not shown). In this case, the thickness of the applied resist film 47 is inevitably non-uniform due to the presence of stepped portions of the groove 46. That is, the resist film 47 formed in the groove 46 is thicker than the resist film 47 formed on the insulating film 45.
Consequently, as shown in FIG. 6, when the resist film 47 is patterned, an exact resist pattern is not obtained due to a deficient exposure time on a thick portion of the resist film 47 and a focus error resulting from a difference in distance between a stepper lens (not shown) and the resist film 47. Thus, the lithographical resolution may deteriorate.
As is shown in FIG. 7, with the resist film 47 used as mask, a contact hole 48 extending to the lower wiring element 42 is formed by subjecting the insulating film 43 to anisotropical etching. Since the resist pattern is not precise, the area of contact with the lower wiring element 42, which is provided by the contact hole 48, decreases. Furthermore, if the pattern on the resist film for forming the wiring groove or contact hole is displaced, the area of contact with the upper wiring element will considerably decrease.
Another problem in the prior art will now be described. FIGS. 8A and 8B are plan views showing a first relationship between the wiring groove 46 and the contact hole 48. In the first relationship, the length of one side of the contact hole 48 is substantially equal to the width of the wiring element formed in the wiring groove 46. FIG. 8A shows a normal position of the contact hole 48, and FIG. 8B shows an abnormal position thereof due to a lithographical alignment error. In FIG. 8B, the contact area between a contact plug (buried in the contact hole) and the wiring element decreases, as compared to the design pattern (FIG. 8A).
According to the above structure, the decrease in contact area between the upper wiring element and the contact plug due to the lithographical alignment error results in an increase in resistance in the circuit operation of the semiconductor apparatus. Consequently, the performance of the semiconductor apparatus deteriorates and the reliability of the device lowers due to an increase in current density.
FIGS. 9A and 9B are plan views showing a second relationship between the wiring groove 46 and the contact hole 48. In the second relationship, the length of one side of the contact hole 48 is greater than the width of the wiring element formed in the wiring groove 46. FIG. 9A shows a normal position of the contact hole 48, and FIG. 9B shows an abnormal position thereof due to a lithographical alignment error. In FIG. 9B, even if an alignment error occurs to some degree in the lithographical step, the width of the contact hole has a tolerance and the contact area according to the design pattern is obtained between the contact plug and the wiring element.
In the case of FIGS. 9A and 9B, if mutually opposed contact plugs are provided on juxtaposed wiring elements, the interval of the wiring elements must be increased because of the limit of lithographical resolution. This problem will now be explained with reference FIGS. 10 and 11.
In an ideal state as shown in FIG. 10, the contact holes 48 shown in FIGS. 8A and 8B can be arranged at an interval of a lithographic resolution limit space L1 for the wiring grooves (or contact holes). In fact, however, the structure shown in FIGS. 9A and 9B which can cancel the alignment error is adopted. In this case, in consideration of the lithographical alignment error, the transverse length of each contact plug is made greater than the width of the wiring element. Thus, the space between the wiring grooves must be set at space L2 which is greater than space L1, with the result that the integration density of semiconductor devices decreases.
The problems of the prior art will now be summarized. In general, in the prior art, when the contact hole for contact between the upper wiring groove for formation of the upper wiring element and the lower wiring element is formed in the interlayer insulating film, all insulating films are deposited and then the resist patterning for forming the groove and the resist patterning for forming the contact hole are carried out. Since the photoresist film is applied to the stepped portion of the groove, the thickness of the resist becomes non-uniform. In the photolithographing step, the precision of the resist pattern deteriorates.
Furthermore, if a mask alignment error occurs, the area of contact between the contact plug and upper wiring decreases. In addition, the bottom and side wall of the contact hole, as well as the bottom and side wall of the wiring groove, are perpendicular to each other, and the coverage of the buried conductor member deteriorates and the lifetime of wiring decreases.
In the case where mutually opposed plugs are provided on juxtaposed wiring elements, if the width of each plug is made greater than that of the wiring element in order to cancel the mask alignment error in the photolithographing step, the space between the wiring elements must be increased because of the limit of lithographical resolution. Consequently, the integration density will decrease.